The invention relates to an addressable memory cell which is composed essentially of a field-effect interrupt transistor and a loop, referred to as a refresh loop, which notably includes two seriesconnected inverters. It also relates to a shift register and a memory having such addressable memory cells.
The invention can be particularly attractively used in the field of large scale integrated circuits (LSI).
An addressable memory cell of the general kind set forth above is known; the known cell is realized in MOS (Metal-Oxide Semiconductor) technology. The known cell consists of on the one hand a MOSFET interrupt transistor whose source is connected to the input terminal of said cell and whose gate is connected to a clock, and on the other hand of a loop which comprises a first inverter which is connected in series with the drain of said interrupt transistor, a second inverter which is connected in series, along the loop, with said first inverter and a second MOSFET transistor which is disposed between the output of the second inverter and the input of the first inverter, and whose gate is connected to a clock which is complementary to that whereto the gate of said MOSFET interrupt transistor is connected. The known addressable memory cell thus comprises two field-effect transistors and requires two clocks.
The general technical problem to be solved in realizing large scale integrated circuits (LSI) is to reduce the number of components of the assemblies performing a given function, for example addressable memory cells as well as shift registers and memories comprising such memory cells. Reduction of the consumption of the circuits is always another problem to solve. Finally, such solutions should preferably be achieved without affecting the performance and the dynamics in particular.
Thus, the technical problem to be solved is to propose an addressable memory cell which consists of on the one hand a field-effect interrupt transistor whose source is connected to the input terminal of said cell and whose gate is connected to a clock, and on the other hand a loop which comprises a first inverter which is connected in series with the drain of said interrupt transistor and whose output is connected to the output terminal of the cell, and a second inverter which is connected in series, along the loop, with said first inverter, which cell should be formed by a smaller number of transistors and have a lower current consumption while the operating frequency should still be high, thus offering substantial savings as regards components and energy when large numbers of memory cells are assembled in shift registers or memories.